Cancel my college entrance examination? The development of the sixth-generation fighter shocked the

Chapter 862

In addition, only after the International Semiconductor Competition is officially over.

The organizers of the International Semiconductor Competition will completely announce all the entries.

Soon, the International Semiconductor Competition officially started.

It also instantly attracted the attention of countless countries.

The first round of the screening competition was almost over.

Next is the elimination round with real casualties.

This elimination round will eliminate two-thirds of the participating teams in this International Semiconductor Competition.

Therefore, this is why most large semiconductor organizations will send so many teams to participate.

Because in this elimination mode of big waves, the more teams there are, the more hope of advancement.

In addition.

The products brought by all national teams will be rated by three intelligent robot referees. After the elimination round is officially established, the national team's entries will be compared and analyzed with all the works recorded in this elimination round.

Then decide whether it is suitable to be put into the elimination round, and if it is suitable, it will be directly put into the elimination round.

If it is not suitable, if the data exceeds too much, it will be directly exempted from the elimination round and advance to the top two thousand, but will not directly compete with the entries of the top two thousand.

Because it is also necessary to compare and comprehensively analyze the data of the two top 1,000 entries to determine whether they are suitable for this level of competition.

If they are suitable, they will be directly rated with the entries of a group of civilian semiconductor teams.

If they are not suitable, it means that the data and comprehensive analysis are too much better than most of the current products.

They will be promoted to the top 1,000 unconditionally.

Subsequent competitions will repeat this rule until the top 64.

Because according to the international semiconductor competitions in previous years, the entries of most national teams basically will not have products with a big gap in the top 64.

And such rules also greatly ensure that during the competition, there will be no unfairness caused by the huge gap between the products of national teams and civilian semiconductor products.

Therefore, this is also an important reason why every country and institution is extremely keen to participate in this competition.

Soon.

The elimination round officially began.

All the participating teams outside the venue were nervously waiting for the final result.

At this time, three intelligent robots were summarizing the information of the works of all participating civilian teams.

Soon, a series of entries from a certain country appeared on their screens!

"Country of entry: Ukrainian Semiconductor Institute."

"Entry: Dynamic Random Access Memory (DRAM)."

"The product development information has been entered, and the design process and design sections are being analyzed:"

"Memory cell design: The memory cell of DRAM is its core component, and its miniaturization and stability must be considered during design. At present, stacked capacitor memory cells have become the mainstream in the industry, especially after the 70nm technology node.

Process determination: Determine the manufacturing process of DRAM, including the preparation of CMOS field effect transistors, the formation of capacitors, etc. Stacked capacitor memory cells are usually formed after CMOS field effect transistors, while deep trench capacitor memory cells are formed before CMOS field effect transistors.

Select high-quality silicon substrates as the basic materials for DRAM.

Prepare other required materials, such as TiN films for capacitor electrodes.

Silicon substrate processing: Pre-process the silicon substrate by cleaning, polishing, etc. to ensure its surface quality.

In the preparation of CMOS field effect transistors, a series of processes are performed on the silicon substrate. CMOS field effect transistors are prepared by process steps, including oxidation, photolithography, doping, etc.

In capacitor formation, capacitors are formed according to the design. For stacked capacitor storage units, capacitors are formed after CMOS field effect transistors; for deep trench capacitor storage units, capacitors are formed before CMOS field effect transistors.

In terms of buried word lines and active area preparation, word lines are buried in the silicon substrate, and active areas are formed on the surface of the carrier. The buried word lines intersect with the active area, and the width in the active area is greater than the width outside the active area.

In other structural preparation areas, other related structures such as transmission tubes are prepared as needed.

The manufactured DRAM is rigorously tested, including performance testing, reliability testing, etc., to ensure that it meets the design requirements.

Verify key indicators such as DRAM read and write speed, storage capacity, and power consumption.

First, select silicon wafers, and select high-quality silicon wafers as the starting material for preparation, and their diameter may reach 200mm or 300mm.

In addition, various reagents are used to clean the silicon wafers in wet cleaning to ensure that there are no impurities on their surfaceDefinition of field effect transistor area

In photolithography, ultraviolet light is used to illuminate the silicon wafer through the mask to form the desired transistor area pattern.

Finally, ion implantation is used to implant different impurities at different locations of the silicon wafer to form N-type and P-type semiconductor regions. These impurities form the key part of the field effect transistor according to their concentration and location.

In terms of gate oxide growth, a thin oxide layer is grown on the silicon wafer as an insulating layer between the gate and the channel.

In this area of ​​polysilicon gate stack formation, polysilicon is deposited on the gate oxide layer and the gate structure is formed through a patterning process. ”

On the screen projection projector of one of the three intelligent robots, there is much more than that.

It even gives suggestions for optimizing and improving this product!

Based on the test results, the design and manufacturing process of DRAM is optimized and improved to improve its performance and stability.

Consider using more advanced process technology and materials to further reduce the size of DRAM and improve integration.

In addition, with the advancement of technology, the size of DRAM storage cells continues to decrease, such as the 14nm process node that has been reached. This requires continuous advancement of manufacturing processes and material technologies.

The second is the refresh mechanism. Since DRAM uses the charge stored in the capacitor to represent data, it needs to be refreshed regularly to maintain the stability of the data. This is An important feature of DRAM is also one of its main differences from other memory technologies.

In terms of integration. The integration of DRAM has an important impact on its performance and application areas. By increasing the integration, larger storage capacity and higher read and write speeds can be achieved.

Finally, in terms of reliability, the reliability of DRAM is crucial to its application. Therefore, in the development process, it is necessary to fully consider various possible failure modes and reliability issues, and take corresponding measures to ensure the reliability of DRAM. ”

“Comprehensive performance score: 70 points”

“Advancedness and future applicability speculation: 50 points.”

“The competitiveness score of this product: 50 points.”

……

“Comprehensive score: 55 points.”

“Analyzing whether it has the qualification for promotion! ”